The present invention relates to a circuit configuration. More specifically, the invention relates to a circuit configuration for converting an input signal into a binary output signal. Furthermore, the present invention relates to a sensor device having a circuit configuration for converting an input signal into a binary output signal.
If an operational amplifier is operated without negative feedback, as shown in FIG. 6A, then a comparator is obtained. The output voltage of such a comparator is: Uamax for U1 greater than U2 and Uamin for U1 less than U2 (see FIG. 6B). On account of the generally high gain of operational amplifiers, the circuit shown in FIG. 6A responds to very small voltage differences U1xe2x88x92U2. It is therefore suitable for comparing two voltages with high precision. If one of the voltages U1 or U2 is put at a fixed reference value, then a comparator is obtained which compares an input voltage with the reference value.
Comparators are used, for example, in the evaluation of sensor signals. Sensors that are operated as switches convert the measurement quantity into an internal electrical signal and form a digital (binary) output signal by comparing the internal electrical signal with an adjustable switching threshold of the comparator used. Such an application of a comparator is shown in U.S. Pat. No. 5,619,137, for example. There, the switching threshold is set by adding bias voltages at the signal inputs of the comparator by current feed-in via resistors lying serially in the input path. However, this bias voltage generation by current feed-in functions only under the precondition that the signal voltage is made available by means of a stage with a sufficient driver capability, for example an operational amplifier or a buffer circuit.
In the evaluation of sensor signals, a demodulation of the signal is often carried out with the aid of capacitances. Particularly in the case of so-called xe2x80x9cchopped Hall sensorsxe2x80x9d, that are shown for example in U.S. Pat. No. 5,621,319, a demodulation with the aid of capacitances is customary in the signal chain of the sensors after the resistive preamplification.
FIG. 5 shows this aspect of the embodiment disclosed in U.S. Pat. No. 5,621,319. The signals from a Hall element H are amplified by an operational amplifier V and passed via switches to capacitors. The signals are subsequently passed via the driver stages V1, V2, V3 and V4 to an adder comprising the resistors R1 and the amplifier K. For compensation of an offset voltage that forms in the Hall element H, the direction of the Hall current IH through the Hall element H is periodically altered, which is indicated by the phases xcfx861 and nxcfx861.
In the evaluation of sensor signals, it is desirable to be able to ensure the lowest possible power consumption of the entire circuit. If a comparator is used in the evaluation of sensor signals, then it is furthermore desirable to be able to ensure the most accurate possible comparison of the internal signal with the preset threshold of the comparator. However, as a result of the driver stages that are conventionally used, for example the driver stages V1, V2, V3 and V4 in U.S. Pat. No. 5,621,319 or the driver stage used in the above-mentioned U.S. Pat. No. 5,619,137, for setting the comparator threshold, the operation of such circuits has hitherto been wherein by a relatively high current consumption and a relatively large inaccuracy due to the offset voltages associated with the driver stages.
It is accordingly an object of the invention to provide a circuit configuration for converting an input signal into a binary output signal which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which reduces or completely avoids the disadvantages of the prior art and, specifically, which has a small current consumption and preferably a small offset error. It is a further, specific object to provide a correspondingly improved sensor device.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for converting an input signal into a binary output signal, comprising:
a comparator;
a clock unit;
a demodulation unit having a plurality of (at least two) capacitors and a plurality of (at least two) switches controlled by the clock unit, the switches connecting the capacitors of the demodulation unit to the comparator and connecting the capacitors to one another; and
the comparator comparing an input signal demodulated by the demodulation unit with at least one reference value and generating the binary output signal.
In other words, the invention provides a circuit configuration for converting an input signal into a binary output signal which has at least one comparator, at least one demodulation unit and at least one clock unit, wherein the demodulation unit has at least one capacitor and at least one switch controlled by the clock unit, which connects the capacitor of the demodulation unit to the comparator, and the comparator compares an input signal demodulated by the demodulation unit with at least one reference value and forms the binary output signal.
With the above and other objects in view there is also provided, in accordance with the invention, a sensor device, comprising:
at least one sensor unit for converting a measurement quantity into an electrical signal; and
at least one circuit configuration as outlined above connected to receive the electrical signal and to convert the electrical signal into a binary output signal.
In accordance with a preferred embodiment of the invention, the sensor unit has at least one Hall element and at least one amplifier stage connected between the Hall element and the circuit configuration.
That is, the invention furthermore provides a sensor device having at least one sensor unit for converting at least one measurement quantity into at least one electrical signal and at least one circuit configuration for converting the electrical signal into at least one binary output signal. The sensor device according to the invention is wherein a circuit configuration according to the invention is provided as the circuit configuration for converting the electrical signal into at least one binary output signal.
The circuit configuration according to the invention has the advantage that the driver stages provided in the prior art are avoided, as a result of which the current consumption of the circuit configuration, the required chip area and the offset errors associated with the driver stages can be significantly reduced.
In accordance with one preferred embodiment, the comparator has an input stage and at least one amplifier stage. In this case, it is particularly preferred if the input stage has at least one differential amplifier.
In accordance with a further preferred embodiment, at least one reference value unit is provided, which provides at least one reference value for the comparator. In this case, it is preferred if the reference value unit has at least one current source. Furthermore, it is particularly preferred if the reference value unit is connected to a reference value input of the comparator. Consequently, the switching threshold of the comparator is not generated by current feed-in in the input path of the comparator upstream of the comparator but rather, from the point of view of the demodulation unit, in the comparator itself. The threshold setting is integrated into the comparator in this sense.
In accordance with a further preferred embodiment, provision is made of at least one unit for the offset adjustment of the comparator. From the point of view of the demodulation unit, a comparator with self-adjustment is thus produced, as a result of which the input stage of the comparator can be dimensioned to be small, so that the signal is essentially not impaired when the capacitances of the demodulation unit are switched in to the comparator. The normally increased offset values from small input stages are virtually entirely eliminated by the unit for offset adjustment of the comparator. Accordingly, the offset error of the comparator is virtually completely eliminated and the overall accuracy of the signal chain is improved. In accordance with a further preferred embodiment, the input capacitance of the signal input of the comparator is less than 20%, preferably less than 10%, of the sum of the capacitances of the capacitors of the demodulation unit at the signal input.
In accordance with a further preferred embodiment, the unit for offset adjustment is connected to the input stage. Furthermore, it is preferred if the unit for offset adjustment has at least one current source. Moreover, it is particularly preferred if the unit for offset adjustment is controlled by the clock unit. In this case, it is particularly preferred if the clock unit controls the switch of the demodulation unit and the unit for offset adjustment in such a way that an offset adjustment of the comparator is carried out while the switch is open.
The offset adjustment is thus preferably carried out before the comparison of the demodulated input signal with the reference value at a point in time at which the comparator is not yet being used. Accordingly, it is preferred if the control signals required for the circuit configuration according to the invention are reduced to two essential signal types, since, preferably, the sample phase of the demodulation unit (switch open) corresponds to the offset adjustment phase of the comparator and the demodulation phase of the demodulation unit (switch closed) corresponds to the comparison phase of the comparator.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration and sensor device, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.